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[Permanent position] Senior verification engineer / team lead
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Senior Hardware & Verification Engineer

Menta -
Sophia Antipolis (06)

Soumettre votre candidature

Détails de l'emploi

Temps plein

Qualifications

Français
UNIX
Git
Anglais
Master
Verilog
Ethernet
Scripting
SystemVerilog
Python

Description complète du poste

Full time
Sophia-Antipolis, France
Help us shape the future of reconfigurable computing — Menta is hiring a Senior Hardware & Verification Engineer to work on next-gen eFPGA IP
Missions

Menta, a leading provider of customizable eFPGA IPs for SoC and ASIC designs, is looking for a skilled and versatile engineer to strengthen its hardware verification team.

You’ll take ownership of a UVM-based verification flow from day one, and contribute to exciting, high-impact hardware development — all within a collaborative R&D team at the heart of the French Riviera tech ecosystem.

Key Responsibilities:
Lead and manage verification flows for complex hardware IP
Support project delivery and long-term IP product integration
Skills & Experience
Solid experience in RTL design and UVM-based verification
Proficiency in Verilog / SystemVerilog / VHDL
Familiarity with EDA tools like Questa, VCS, or Xcelium
Knowledge of SoC IPs (Ethernet, USB, DDR, etc.)
Strong scripting skills (Python, TCL), Unix environment, and Git
Fluent in English; French is a plus
Master’s degree or equivalent in a relevant field
Environment
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Our values

MENTA’s technology offers a highly reliable solution for all those involved in innovation, thanks to its high degree of customization to different technologies and customer needs, the performance and durability it offers to electronic chips, combined with unbeatable production times.

Our vision is one of responsible progress, fueled by a pioneering spirit of excellence and self-improvement, creating value.
Accelerating progress through our technologies means meeting the challenges of the future together.

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python emplois - nice, b8

Senior Hardware & Verification Engineer

Post-Doctoral Research Visit F/M Computational design of next-generation optical metasurfaces

Post-Doctoral Research Visit F/M Operator learning for the time-harmonic Maxwell equations

Physical Implementation Engineer

Ingénieur Cloud-DevOps (H/F)

Senior FPGA Engineer

Site Reliability Engineer (expérimenté, CDI)

[Permanent position] Senior verification engineer / team lead

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