Salaires pour le poste Verification Engineer, Auvergne-Rhône-Alpes

Excellent communication skills and a proactive mindset. Knowledge of semiconductor, ASIC, FPGA, or hardware verification workflows.

Experience with formal and dynamic verification. Experience in block level and sub-system or top level verification. Proficiency in SystemVerilog and UVM.

Experience with formal and dynamic verification. Experience in verification of coherent systems. Develop and maintain verification environments using…

Strong communication and interpersonal skills to effectively collaborate with cross-functional teams. Solid knowledge and experience in dynamic thermal…

Formal-Friendly Design: Partner with VU microarchitects during early-stage RTL development to drive formal-friendly coding styles and structural design patterns…

Il y a 6 jours

Nous accordons plus d'importance à la passion et à l’état d’esprit qu'à l'expérience. Certification ou compétence en communication technique ;

Il y a 3 jours